Full course coming soon

System-Level Chip Design: Packaging, Partitioning, and Performance

7 chapters · 32 lessons

1. 1. Why Data Movement Limits Modern Processors

   4 lessons

   Understand how power, latency, and bandwidth constraints shifted chip design from transistor scaling to system-level architecture.

2. 2. Partitioning Functions Across Dies

   5 lessons

   Learn the architectural principles for deciding which functions belong on separate dies and how to connect them.

3. 3. Advanced Packaging Interconnect Technologies

   4 lessons

   Explore the physical methods for connecting dies, from wire bonding to hybrid bonding, and their performance characteristics.

4. 4. Thermal and Power Management in 3D Stacks

   5 lessons

   Analyze how stacking affects heat dissipation and power delivery, and learn mitigation strategies.

5. 5. Heterogeneous Compute and Specialization

   4 lessons

   Understand how mixing CPU, GPU, accelerator, and efficiency cores in one package improves performance per watt.

6. 6. Application-Specific Packaging Strategies

   5 lessons

   Map packaging decisions to real-world constraints in mobile, data center, automotive, and edge deployments.

7. 7. Evaluating Packaging Tradeoffs in Product Design

   5 lessons

   Develop frameworks for deciding when advanced packaging justifies its cost and complexity in your product roadmap.